Sciweavers

11 search results - page 1 / 3
» Stage-skip pipeline: a low power processor architecture usin...
Sort
View
ISLPED
1996
ACM
143views Hardware» more  ISLPED 1996»
13 years 9 months ago
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer
Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Ko...
WMPI
2004
ACM
13 years 10 months ago
Addressing mode driven low power data caches for embedded processors
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
Ramesh V. Peri, John Fernando, Ravi Kolagotla
HPCA
2003
IEEE
14 years 5 months ago
Power-Aware Control Speculation through Selective Throttling
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
Juan L. Aragón, José González...
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 9 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
TVLSI
2010
12 years 11 months ago
A Low-Power DSP for Wireless Communications
This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture--Signal processi...
Hyunseok Lee, Chaitali Chakrabarti, Trevor N. Mudg...