25 search results - page 4 / 5 » Standby Leakage Power Reduction Technique for Nanoscale CMOS... |
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
ISLPED
2003
ACM
13 years 9 months ago
2003
ACM
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...