31 search results - page 2 / 7 » Statistical gate delay model for Multiple Input Switching |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
ANSS
2003
IEEE
13 years 10 months ago
2003
IEEE
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate a...
ATS
2009
IEEE
13 years 3 months ago
2009
IEEE
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
VTS
2007
IEEE
13 years 11 months ago
2007
IEEE
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...