12 search results - page 1 / 3 » Storage Assignment to Decrease Code Size |
PLDI
1995
ACM
13 years 8 months ago
1995
ACM
DSP architectures typically provide indirect addressing modes with auto-increment and decrement. In addition, indexing mode is not available, and there are usually few, if any, ge...
CC
2004
Springer
13 years 10 months ago
2004
Springer
An important issue in embedded systems design is the size of programs. As computing devices decrease in size, yet with more and more functions, better code size optimizations are i...
CC
2003
Springer
13 years 10 months ago
2003
Springer
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...
CASES
2004
ACM
13 years 10 months ago
2004
ACM
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....