48 search results - page 1 / 10 » Strategies for mapping dataflow blocks to distributed hardwa... |
MICRO
2008
IEEE
13 years 4 months ago
2008
IEEE
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
CODES
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
SBACPAD
2005
IEEE
13 years 10 months ago
2005
IEEE
The Data-Flow Graph (DFG) of a parallel application is frequently used to take scheduling decisions, based on the information that it models (dependencies among the tasks and volu...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper we propose an embedded software design flow, which starts from an UML model and provides automatic mapping to other models like Simulink or finite-state machines (FS...
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several meth...