871 search results - page 1 / 175 » Streaming Reduction Circuit |
DSD
2009
IEEE
13 years 8 months ago
2009
IEEE
—Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when m...
CORR
2008
Springer
13 years 4 months ago
2008
Springer
Abstract. We study rational streams (over a field) from a coalgebraic perspective. Exploiting the finality of the set of streams, we present an elementary and uniform proof of the ...
CF
2005
ACM
13 years 6 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents a realizable RLMC1 reduction algorithm for extracted interconnect circuits based on two effective approaches: RL branch reduction and RC/LC node reduction. Our...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...