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    DAC
    1996
    ACM
    125views Computer Architecture» more  DAC 1996»
    Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
    13 years 9 months ago
    Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
    Download  cadlab.cs.ucla.edu
    In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...
    Jason Cong, Yean-Yow Hwang
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    DAC
    2000
    ACM
    114views Computer Architecture» more  DAC 2000»
    Depth optimal incremental mapping for field programmable gate arrays
    14 years 5 months ago
    Depth optimal incremental mapping for field programmable gate arrays
    Download  cadlab.cs.ucla.edu
    In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...
    Jason Cong, Hui Huang
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    FPGA
    2001
    ACM
    145views FPGA» more  FPGA 2001»
    Simultaneous logic decomposition with technology mapping in FPGA designs
    13 years 9 months ago
    Simultaneous logic decomposition with technology mapping in FPGA designs
    Download  cadlab.cs.ucla.edu
    Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
    Gang Chen, Jason Cong
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    FPGA
    2006
    ACM
    155views FPGA» more  FPGA 2006»
    Improvements to technology mapping for LUT-based FPGAs
    13 years 8 months ago
    Improvements to technology mapping for LUT-based FPGAs
    Download  www.eecs.berkeley.edu
    The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
    Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
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    FPGA
    2007
    ACM
    185views FPGA» more  FPGA 2007»
    Power-aware FPGA logic synthesis using binary decision diagrams
    13 years 11 months ago
    Power-aware FPGA logic synthesis using binary decision diagrams
    Download  www.ecs.umass.edu
    Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
    Kevin Oo Tinmaung, David Howland, Russell Tessier
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