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DAC
1995
ACM
13 years 9 months ago
Hierarchical Optimization of Asynchronous Circuits
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Bill Lin, Gjalt G. de Jong, Tilman Kolks
ISPD
2005
ACM
188views Hardware» more  ISPD 2005»
13 years 11 months ago
A semi-persistent clustering technique for VLSI circuit placement
Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant p...
Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, S...
ACSD
2005
IEEE
90views Hardware» more  ACSD 2005»
13 years 11 months ago
Improved Decomposition of STGs
Signal Transition Graphs (STGs) are a version of Petri nets for the specification of asynchronous circuit behaviour. It has been suggested to decompose such a specification as a...
Walter Vogler, Ben Kangsah
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
14 years 1 days ago
Multiple-Width Bus Partitioning Approach to Datapath Synthesis
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
Arash Ahmadi, Mark Zwolinski
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
13 years 10 months ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...