In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hon...
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In thisp...
Parallel simulation is expected to speed up simulation run time in a signi cant way. This paper describes a framework that is used to evaluate the performance of parallel simulati...
— We present an efficient method for automatically extracting unified amplitude/phase macromodels of arbitrary oscillators from their SPICE-level circuit descriptions. Such com...