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» Symbolic analysis of analog circuits with hard nonlinearity
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FMCAD
2004
Springer
13 years 10 months ago
Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
Mohammad Awedh, Fabio Somenzi
ASPDAC
2008
ACM
174views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty
In modern circuit design, it is difficult to provide reliable parametric yield prediction since the real distribution of process data is hard to measure. Most existing approaches ...
Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang
SIGCSE
2009
ACM
143views Education» more  SIGCSE 2009»
13 years 11 months ago
Thinking about computational thinking
Jeannette Wing’s call for teaching Computational Thinking (CT) as a formative skill on par with reading, writing, and arithmetic places computer science in the category of basic...
James J. Lu, George H. L. Fletcher
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
13 years 10 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...