48 search results - page 3 / 10 » Symbolic functional and timing verification of transistor-le... |
VLSID
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
GLVLSI
2002
IEEE
13 years 10 months ago
2002
IEEE
As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) ...
EURODAC
1994
IEEE
13 years 10 months ago
1994
IEEE
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and ...
ASYNC
1997
IEEE
13 years 9 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...