61 search results - page 1 / 13 » Synthesis of Selectively Clocked Skewed Logic Circuits |
ISQED
2002
IEEE
13 years 10 months ago
2002
IEEE
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
ISCAS
1994
IEEE
13 years 9 months ago
1994
IEEE
