To construct complete systems on silicon, application specic DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access con...
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, E...
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...