Sciweavers

12 search results - page 3 / 3
» Synthesis of pipelined DSP accelerators with dynamic schedul...
Sort
View
IPPS
2006
IEEE
13 years 10 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
ISCA
2007
IEEE
152views Hardware» more  ISCA 2007»
13 years 11 months ago
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
Sanjeev Kumar, Christopher J. Hughes, Anthony D. N...