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» System chip test: how will it impact your design
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VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 5 days ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
SIGUCCS
2000
ACM
13 years 10 months ago
Ills Cured with a Dose of Remedy
We presented a paper in Denver that addressed our Remedy design process. At that time we talked about our current development process, but we hadn't implemented the product a...
Michael Critchfield, Michael Murray
DATE
2003
IEEE
135views Hardware» more  DATE 2003»
13 years 11 months ago
Creating Value Through Test
Test is often seen as a necessary evil; it is a fact of life that ICs have manufacturing defects and those need to be filtered out by testing before the ICs are shipped to the cu...
Erik Jan Marinissen, Bart Vermeulen, Robert Madge,...
HICSS
2006
IEEE
105views Biometrics» more  HICSS 2006»
13 years 12 months ago
The Impact of Design Moves on Platform Adoption: The Case of Microsoft Windows OS
How soon will firms form alliances with a platform provider? What factors impact the decision and the speed with which firms first move into partnerships with a platform provider ...
Xiang Liu, Chi-Hyon Lee, Bala Iyer
CASES
2006
ACM
13 years 11 months ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...