Sciweavers

897 search results - page 2 / 180
» System-Level Design for FPGAs
Sort
View
DAC
2005
ACM
14 years 6 months ago
Logic block clustering of large designs for channel-width constrained FPGAs
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
Marvin Tom, Guy G. Lemieux
DATE
2009
IEEE
136views Hardware» more  DATE 2009»
14 years 6 hour ago
Reconfigurable circuit design with nanomaterials
—It is generally acknowledged that nanoelectronics will eventually replace traditional silicon CMOS in high-performance integrated circuits. To that end, considerable investments...
Chen Dong, Scott Chilstedt, Deming Chen
SAC
2003
ACM
13 years 10 months ago
ARCHITECT-R: A System for Reconfigurable Robots Design
An increasing interest in the design of mobile robots has been observed in recent years, which is mainly motivated by technological advances that may allow their application to co...
R. A. Gonçalves, P. A. Moraes, João ...
FCCM
2004
IEEE
133views VLSI» more  FCCM 2004»
13 years 9 months ago
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
Intrusion detection for network security is a computation intensive application demanding high system performance. System level design, a relatively unexplored field in this area,...
Zachary K. Baker, Viktor K. Prasanna
SAMOS
2007
Springer
13 years 11 months ago
Design Space Exploration of Configuration Manager for Network Processing Applications
—Current FPGAs provide a powerful platform for network processing applications. The main challenge is the exploitation of the reconfiguration to increase the performance of the s...
Christoforos Kachris, Stamatis Vassiliadis