16 search results - page 1 / 4 » System-Level Synthesis of Low-Power Hard Real-Time Systems |
DAC
1997
ACM
13 years 9 months ago
1997
ACM
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
RTSS
1998
IEEE
13 years 9 months ago
1998
IEEE
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
RTAS
2000
IEEE
13 years 9 months ago
2000
IEEE
—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...
DAC
1995
ACM
13 years 8 months ago
1995
ACM
—We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are cons...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...