119 search results - page 3 / 24 » Targeting Tiled Architectures in Design Exploration |
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many til...
TPDS
2008
13 years 5 months ago
2008
Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern app...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
CODES
2001
IEEE
13 years 9 months ago
2001
IEEE
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
MSE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper summarizes two graduate-level class projects in EE201A/EE298 (VLSI Architectures and Design Methods) at the University of California, Los Angeles (UCLA). The purpose of...