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» Techniques for Formal Verification of Digital Systems: A Sys...
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FDL
2007
IEEE
13 years 9 months ago
Transactor-based Formal Verification of Real-time Embedded Systems
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
Daniel Karlsson, Petru Eles, Zebo Peng
ISCAS
2003
IEEE
135views Hardware» more  ISCAS 2003»
13 years 11 months ago
Formal verification of LTL formulas for SystemC designs
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
Daniel Große, Rolf Drechsler
HYBRID
2007
Springer
13 years 9 months ago
Safety Verification of an Aircraft Landing Protocol: A Refinement Approach
Abstract. In this paper, we propose a new approach for formal verification of hybrid systems. To do so, we present a new refinement proof technique, a weak refinement using step in...
Shinya Umeno, Nancy A. Lynch
DATE
2004
IEEE
97views Hardware» more  DATE 2004»
13 years 9 months ago
A Formal Verification Methodology for Checking Data Integrity
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
Yasushi Umezawa, Takeshi Shimizu
CAV
1990
Springer
114views Hardware» more  CAV 1990»
13 years 9 months ago
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
Ternary system modeling involves extending the traditional set of binary values
Randal E. Bryant, Carl-Johan H. Seger