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PARELEC
2002
IEEE
13 years 10 months ago
Techniques for Optimization of Net Algorithms
In this paper, techniques for optimization of net algorithms describing parallel asynchronous computations and derived from cycling and branching behavioral descriptions are prese...
Anatoly Prihozhy, Daniel Mlynek, Michail Solomenni...
ICANNGA
2007
Springer
100views Algorithms» more  ICANNGA 2007»
13 years 11 months ago
Genetic-Greedy Hybrid Approach for Topological Active Nets Optimization
In this paper we propose a genetic and greedy algorithm combination for the optimization of the Topological Active Nets (TAN) model. This is a deformable model used for image segme...
José Santos, Óscar Ibáñ...
ASPDAC
2006
ACM
102views Hardware» more  ASPDAC 2006»
13 years 11 months ago
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks
— Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the numbe...
Zhuo Li, Weiping Shi
TCAD
2008
119views more  TCAD 2008»
13 years 5 months ago
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
Abstract-- In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT) algorithm called FLUTE. FLUTE is based on pre-computed lookup table to make RS...
Chris C. N. Chu, Yiu-Chung Wong
VLSID
2002
IEEE
100views VLSI» more  VLSID 2002»
13 years 10 months ago
Layout-Driven Timing Optimization by Generalized De Morgan Transform
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
Supratik Chakraborty, Rajeev Murgai