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VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 5 months ago
Temperature and Process Variations Aware Power Gating of Functional Units
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sar...
VLSID
2008
IEEE
111views VLSI» more  VLSID 2008»
14 years 5 months ago
Power Reduction of Functional Units Considering Temperature and Process Variations
Continuous technology scaling has resulted in an increase in both, the power density as well as the variation in device dimensions (process variations) of the manufactured process...
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj...
TVLSI
2008
176views more  TVLSI 2008»
13 years 4 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
INTEGRATION
2008
96views more  INTEGRATION 2008»
13 years 4 months ago
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Vi...
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
13 years 11 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie