37 search results - page 2 / 8 » Test Enrichment for Path Delay Faults Using Multiple Sets of... |
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
VTS
2000
IEEE
13 years 9 months ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
ATS
2005
IEEE
13 years 10 months ago
2005
IEEE
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...