4 search results - page 1 / 1 » Test Pattern Generation for Realistic Bridge Faults in CMOS ... |
ITC
1991
IEEE
13 years 8 months ago
1991
IEEE
Two approaches have been used to balance the cost of generating e ective tests for ICs and the need to increase the ICs' quality level. The rst approach favorsusing high-leve...
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
VTS
1996
IEEE
13 years 8 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
DAC
2000
ACM
13 years 9 months ago
2000
ACM
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...