145 search results - page 1 / 29 » Test Resource Partitioning and Optimization for SOC Designs |
VTS
2003
IEEE
13 years 10 months ago
2003
IEEE
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
ET
2002
13 years 4 months ago
2002
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...