142 search results - page 2 / 29 » Test architecture design and optimization for three-dimensio... |
MOBIHOC
2009
ACM
13 years 11 months ago
2009
ACM
Low-connectivity and full-coverage three dimensional Wireless Sensor Networks (WSNs) have many real-world applications. By low connectivity, we mean there are at least k disjoint ...
TVLSI
2008
13 years 4 months ago
2008
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
DSD
2010
IEEE
13 years 3 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...