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» Test generation for designs with multiple clocks
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ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Efficient BMC for Multi-Clock Systems with Clocked Specifications
- Current industry trends in system design -- multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with...
Malay K. Ganai, Aarti Gupta
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
13 years 10 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
DSD
2008
IEEE
115views Hardware» more  DSD 2008»
13 years 11 months ago
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA
We propose a method to efficiently design a “parity generator”, which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designe...
Petr Fiser, Pavel Kubalík, Hana Kubatova
DAC
2000
ACM
14 years 5 months ago
Power minimization using control generated clocks
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
M. Srikanth Rao, S. K. Nandy
FMICS
2008
Springer
13 years 6 months ago
Extending Structural Test Coverage Criteria for Lustre Programs with Multi-clock Operators
Lustre is a formal synchronous declarative language widely used for modeling and specifying safety-critical applications in the elds of avionics, transportation or energy productio...
Virginia Papailiopoulou, Laya Madani, Lydie du Bou...