143 search results - page 3 / 29 » Test generation for designs with multiple clocks |
FPGA
2008
ACM
13 years 7 months ago
2008
ACM
This paper introduces a method of constructing random number generators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. ...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
ARVLSI
1999
IEEE
13 years 10 months ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
DATE
2007
IEEE
13 years 12 months ago
2007
IEEE
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
DATE
2007
IEEE
13 years 12 months ago
2007
IEEE
3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers....