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» Test generation in VLSI circuits for crosstalk noise
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ITC
1998
IEEE
120views Hardware» more  ITC 1998»
13 years 9 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
DFT
2002
IEEE
108views VLSI» more  DFT 2002»
13 years 9 months ago
A Test-Vector Generation Methodology for Crosstalk Noise Faults
Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park
TCAD
2002
115views more  TCAD 2002»
13 years 4 months ago
Analytical models for crosstalk excitation and propagation in VLSI circuits
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
ICCD
2001
IEEE
213views Hardware» more  ICCD 2001»
14 years 1 months ago
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
Payam Heydari, Massoud Pedram
ICCAD
1995
IEEE
163views Hardware» more  ICCAD 1995»
13 years 8 months ago
Signal integrity optimization on the pad assignment for high-speed VLSI design
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
Kai-Yuan Chao, D. F. Wong