244 search results - page 3 / 49 » Testing Digital Circuits with Constraints |
ITC
1996
IEEE
13 years 10 months ago
1996
IEEE
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
VTS
1999
IEEE
13 years 10 months ago
1999
IEEE
This paper presents an algorithm based on testability measurement for test point insertion of mixed-signal circuits. Two transfer function models compatible with analog models are...
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE