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DATE
2008
IEEE
108views Hardware» more  DATE 2008»
13 years 12 months ago
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns
CASP, Concurrent Autonomous chip self-test using Stored test Patterns, is a special kind of self-test where a system tests itself concurrently during normal operation without any ...
Yanjing Li, Samy Makar, Subhasish Mitra
VTS
1998
IEEE
88views Hardware» more  VTS 1998»
13 years 9 months ago
Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
Bruce F. Cockburn, Albert L.-C. Kwong
ITC
1993
IEEE
110views Hardware» more  ITC 1993»
13 years 9 months ago
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A...
TCAD
2008
114views more  TCAD 2008»
13 years 5 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty
VTS
2007
IEEE
89views Hardware» more  VTS 2007»
13 years 11 months ago
Test Set Reordering Using the Gate Exhaustive Test Metric
When a test set size is larger than desired, some patterns must be dropped. This paper presents a systematic method to reduce test set size; the method reorders a test set using t...
Kyoung Youn Cho, Edward J. McCluskey