14 search results - page 2 / 3 » Testing and Diagnosis of Interconnect Structures in FPGAs |
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
This paper presents a new approach for diagnosing stuck-at and short faults in interconnects whose layouts are known. This structural approach exploits dierent graph coloring and ...
ET
2006
13 years 5 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
FPGA
2006
ACM
13 years 9 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...