100 search results - page 20 / 20 » The Sizing Rules Method for Analog Integrated Circuit Design |
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
ISCA
2007
IEEE
14 years 18 days ago
2007
IEEE
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lag...
GLVLSI
2010
IEEE
13 years 8 months ago
2010
IEEE
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...