3 search results - page 1 / 1 » The Y-Architecture for On-Chip Interconnect: Analysis and Me... |
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...