55 search results - page 2 / 11 » The design and implementation of a low-latency on-chip netwo... |
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
CCGRID
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a new low-level communication subsystem called Nemesis. Nemesis has been designed and implemented to be scalable and efficient both in the intranode communica...
ARC
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. In this paper, we present a systematic design and implementation of reconfigurable interconnects on demand. The proposed on-chip interconnection network provides identic...
IEEEPACT
2009
IEEE
13 years 12 months ago
2009
IEEE
—Oblivious routing can be implemented on simple router hardware, but network performance suffers when routes become congested. Adaptive routing attempts to avoid hot spots by re-...
ASAP
2007
IEEE
13 years 9 months ago
2007
IEEE
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...