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» The design of a low power asynchronous multiplier
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ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
13 years 10 months ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber
ASYNC
2004
IEEE
133views Hardware» more  ASYNC 2004»
13 years 8 months ago
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
One of the main reasons for using asynchronous design is that it offers the opportunity to exploit the datadependent latency of many operations in order to achieve low-power, high...
Aristides Efthymiou, W. Suntiamorntut, Jim D. Gars...
APCCAS
2006
IEEE
229views Hardware» more  APCCAS 2006»
13 years 11 months ago
Low Power Combinational Multipliers using Data-driven Signal Gating
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
Nima Honarmand, Ali Afzali-Kusha
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 1 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
GLVLSI
1998
IEEE
134views VLSI» more  GLVLSI 1998»
13 years 9 months ago
Low-Power Design of Finite Field Multipliers for Wireless Applications
Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasr...