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» The impact of the nanoscale on computing systems
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DSN
2005
IEEE
13 years 11 months ago
Reversible Fault-Tolerant Logic
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiti...
P. Oscar Boykin, Vwani P. Roychowdhury
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 2 months ago
A Probabilistic-Based Design Methodology for Nanoscale Computation
As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research p...
R. Iris Bahar, Joseph L. Mundy, Jie Chen
IJON
2011
90views more  IJON 2011»
12 years 8 months ago
Fault tolerant machine learning for nanoscale cognitive radio
We introduce a machine learning based classifier that identifies free radio channels for cognitive radio. The architecture is designed for nanoscale implementation, under nanosc...
Joni Pajarinen, Jaakko Peltonen, Mikko A. Uusitalo
VLSID
2007
IEEE
85views VLSI» more  VLSID 2007»
14 years 5 months ago
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
Elias Kougianos, Saraju P. Mohanty
GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...