48 search results - page 3 / 10 » The synthesis of combinational logic to generate probabiliti... |
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
FPL
2006
Springer
13 years 9 months ago
2006
Springer
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
ITC
1994
IEEE
13 years 9 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
ISPD
2012
ACM
12 years 25 days ago
2012
ACM
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
CORR
2008
Springer
13 years 5 months ago
2008
Springer
We describe Haskell implementations of interesting combinatorial generation algorithms with focus on boolean functions and logic circuit representations. First, a complete exact c...