115 search results - page 22 / 23 » The synthesis of cyclic combinational circuits |
ENTCS
2008
13 years 5 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
TCAD
2002
13 years 5 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
ICCD
1997
IEEE
13 years 9 months ago
1997
IEEE
Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practica...
CODES
2008
IEEE
14 years 7 days ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
FMCAD
2000
Springer
13 years 9 months ago
2000
Springer
Image computation nds wide application in VLSI CAD, such as state reachability analysis in formal veri cation and synthesis, combinational veri cation, combinational and sequential...