21 search results - page 2 / 5 » Thermal via planning for 3-D ICs |
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
3-D IC has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-on-chip or system-in-package solutions. A cr...
ICCD
2007
IEEE
14 years 2 months ago
2007
IEEE
One of the biggest challenges in 3D stacked IC design is heat dissipation. Incorporating thermal vias is a promising method for reducing the temperatures of 3D ICs. The bonding st...
ISLPED
2006
ACM
13 years 11 months ago
2006
ACM
All existing methods for thermal-via allocation are based on a steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and ...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract— 3D circuits have the potential to improve performance over traditional 2D circuits by reducing wirelength and interconnect delay. One major problem with 3D circuits is ...