10 search results - page 1 / 2 » Thermal-aware high-level synthesis based on network flow met... |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reli...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...