40 search results - page 7 / 8 » Timing Driven Placement for Large Standard Cell Circuits |
FCCM
2005
IEEE
13 years 11 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
ICCD
2007
IEEE
14 years 2 months ago
2007
IEEE
We present new techniques for explicit constraint satisfaction in the incremental placement process. Our algorithm employs a Lagrangian Relaxation (LR) type approach in the analyt...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
HEURISTICS
2002
13 years 5 months ago
2002
In this paper, we present the parallelization of tabu search on a network of workstations using PVM. Two parallelization strategies are integrated: functional decomposition strate...
TCAD
2008
13 years 5 months ago
2008
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...