28 search results - page 5 / 6 » Timing Driven Placement for Quasi Delay-Insensitive Circuits |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
VLSID
2002
IEEE
13 years 10 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
ISPD
2009
ACM
13 years 12 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...