72 search results - page 2 / 15 » Timing Optimization of Logic Network Using Gate Duplication |
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
FPL
2009
Springer
13 years 10 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
VLSID
2002
IEEE
13 years 10 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
ICON
2007
IEEE
13 years 11 months ago
2007
IEEE
Several components contribute to handover delay of Mobile IPv6, namely, movement detection time, address configuration time, binding registration time, and route optimization time....