718 search results - page 2 / 144 » Timing Yield Calculation Using an Impulse-Train Approach |
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
PATMOS
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
SCP
2008
13 years 4 months ago
2008
We proposed a method to quantify the yield of an IT-investment portfolio in an environment of uncertainty and risk. For various common implementation scenarios such as growing dem...
DFT
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design whi...