16 search results - page 2 / 4 » Timing and Crosstalk Driven Area Routing |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
ISPD
2005
ACM
13 years 11 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
FPGA
1999
ACM
13 years 9 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
GLVLSI
2005
IEEE
13 years 11 months ago
2005
IEEE
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Abstract--In this paper, the problem of bus driven floorplanning is addressed. Given a set of modules and bus specifications, a floorplan solution including the bus routes will be ...