118 search results - page 1 / 24 » Timing constraint specification and synthesis in behavioral ... |
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
DAC
2000
ACM
13 years 9 months ago
2000
ACM
In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking ...
LCPC
2001
Springer
13 years 9 months ago
2001
Springer
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...