93 search results - page 1 / 19 » Timing optimization of FPGA placements by logic replication |
DAC
2003
ACM
14 years 5 months ago
2003
ACM
DAC
2004
ACM
14 years 5 months ago
2004
ACM
We present a set of techniques for placement-coupled, timingdriven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timingdrive...
FPGA
2004
ACM
13 years 8 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance...
EH
2004
IEEE
13 years 8 months ago
2004
IEEE
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize ...