51 search results - page 10 / 11 » Timing variation-aware high-level synthesis |
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
ICCAD
1997
IEEE
13 years 10 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...