4 search results - page 1 / 1 » Timing-driven cell layout de-compaction for yield optimizati... |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as cr...
ISPD
2010
ACM
13 years 12 months ago
2010
ACM
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
DATE
2009
IEEE
13 years 9 months ago
2009
IEEE
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...