Physically clustered forward body biasing for variability compensation in nanometer CMOS design

Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have focused on adaptive post-fabrication tuning approaches to mitigate this problem. Adaptive Body Bias (ABB) is one of the most successful tuning "knobs" in use today in high-performance custom design. Through forward body bias (FBB), the threshold voltage of the CMOS devices can be reduced after fabrication to bring the slow dies back to within the range of acceptable specs. FBB is usually applied with a very coarse core-level granularity at the price of a significantly increased leakage power. In this paper, we propose a novel, physically clustered FBB scheme on row-based standardcell layout style that enables selective forward body biasing of only of the rows that contain most timing critical gates, thereby reducing leakage power overhead. We propose exact and heuristic algorithms to partition the ...

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii
• Keywords: Body Bias, DATE 2009, Hardware, Leakage Power, Leakage Power Overhead